What is the Polysilicon Depletion Effect?

When we look at the gate material choices, it’s clear why polysilicon was chosen over metal initially. It had a favorable interface with gate oxide (SiO₂). But I noticed that the low conductivity of polysilicon led to issues like charge accumulation delays. By doping it with N-type or P-type impurities, we could improve conductivity, but it still wasn’t perfect.

You know, polysilicon is made up of small silicon crystals, which is different from monocrystalline silicon used in other semiconductor electronics. It has its pros and cons. The low conductivity of the polysilicon layer causes delays in channel formation, which can mess up circuit performance. We really needed the high-k metal gates to address this.

In my experience, doped polysilicon gates have several disadvantages. For example, in an nMOS transistor, when you apply a positive field to the gate, the majority carriers get scattered, forming a depletion region. This can cause significant transistor variability, especially with different fabrication processes. Switching to metal gates has really helped us mitigate these issues.

We’ve seen that as devices scaled down to 32-28nm nodes, the use of metal gates became more common. High-k dielectric metal gate (HKMG) integration was a game changer. I remember Intel’s press kit in 2011 showing how they used this technology to improve performance. Metal gates are now preferred over polysilicon to avoid variations in the threshold voltage and other issues.