We fill via holes with tungsten in VLSI technology because tungsten has low stress and high resistance to electromigration, which makes it a reliable material for ensuring good electrical connections. I think you can see how important these properties are for maintaining the integrity of the connections in integrated circuits. Additionally, tungsten adheres well to materials like silicon, aluminium, and silicide’s, which helps in creating strong, self-aligned structures.(Image source)
Challenges associated with using tungsten for via hole filling
However, there are challenges associated with using tungsten for via hole filling. One major issue is that tungsten does not stick well to SiO2 unless there are nucleation sites available. To avoid unwanted tungsten growth on SiO2 surfaces, we need to ensure proper cleaning procedures. Another challenge is the potential for tungsten to laterally encroach under the oxide, which can cause loss of selectivity and form “worm holes” in silicon. This can lead to defects and reliability issues.
Aspect Ratio of Vias
Moreover, as the aspect ratio of the vias increases, shadowing effects during tungsten deposition can cause voids at the top edges of the vias. These voids can create weak spots in the connections. To mitigate this, reactive sputter etch can be used to open up the voids. Despite these challenges, the benefits of using tungsten, such as its resistance to electromigration and its compatibility with IC technologies, make it a valuable material for via hole filling in VLSI technology.
