As I delve into the world of semiconductor manufacturing, I’m constantly amazed at the relentless pursuit of miniaturization. Today, the semiconductor industry is aggressively moving toward printing ever-decreasing feature sizes, pushing lithography to extend its resolution capabilities significantly. Optical lithography for the 32nm half-pitch node has been demonstrated, but by 2018, volume manufacturing of the 16 to 22nm half-pitch nodes was anticipated.
EUV vs. DPL for Sub-32nm Nodes
EUV is a candidate to shrink feature sizes below 32nm, but while there have been significant improvements, it may not be mature enough to become the mainstream technology. Therefore, double-patterning lithography (DPL) is considered the only feasible alternative for sub-32nm nodes.
The Mechanism of Double-Patterning Lithography
In DPL, sub-resolution patterns of the original layout are decomposed into two masks, each of which is printed by an independent lithography process. This increases the pitch size and thus improves the common process window.
Different Schemes in DPL
There are three DPL schemes that draw the most attention for IC manufacturing: litho-etch-litho-etch (LELE), litho-freeze-litho-etch (LFLE), and self-aligned double patterning (SADP). The LELE method consists of two complete lithography steps, each followed by an etching process. Compared with other DPL methods, LELE is simpler but requires more accurate overlay control.
The Complexities of LFLE and SADP
LFLE freezes the latent image of the first exposure, then adds a second resist layer immediately on top for the second exposure. The resist pattern is etched only once after developing the resist. Although LFLE uses fewer process steps, its required processes are complex and not yet mature. SADP, on the other hand, is fairly robust against overlay error but is currently applied only for patterning regular configurations.
LELE’s Initial Preference and Overlay Sensitivity
Among all the DPL strategies, the LELE method was originally preferred due to its layout decomposition and process simplicity. However, its high sensitivity to overlay has prompted the search for another method less sensitive to imaging overlay between the two exposures.
SADP’s Role in Advanced Lithography
SADP, mainly used in FLASH-specific applications, is being considered for M1/M2 interconnects. To this end, the basic SADP method followed by a lithography step is used to trim part of spacers and print irregular patterns. The achievable pitch resolution of this method depends on how litho-friendly the Trim mask is.
Challenges in Layout Decomposition
Layout decomposition, a major challenge for all DPL methods, can be translated into a graph coloring problem. Unfortunately, for a complex 2D layout, the corresponding pitch-conflict graph is not always two-colorable.
Stitch Minimization in LELE and SADP
To decompose a non-colorable structure, some of its polygons need to be split between two masks. However, since this pattern stitching increases the sensitivity of LELE masks to overlay error, stitch minimization is a primary objective for layout decomposition. In SADP, pattern splitting is not even permitted because it causes unresolvable gap failures.
EDA Solutions for Layout Decomposition
There are two categories of EDA solutions to perform layout decomposition. The first approach is post-layout decomposition, which finds a valid decomposition with a minimum number of stitches. The second approach is correct-by-construction, where decomposition is performed simultaneously with the layout patterns being finalized.
Addressing SADP-Specific Requirements
None of the proposed EDA solutions considers SADP-specific requirements. However, a smart decomposition can play a significant role in designing litho-friendly Trim masks and consequently improving the overall printability of layout.
The Need for Litho-Friendly SADP Decomposition
In this article, we discuss the effective parameters in the printability of SADP decomposed layouts. We also propose an ILP-based decomposition method designed to avoid decomposition conflicts and improve the overall printability of layout patterns. To our best knowledge, this is the first attempt to consider SADP-specific requirements in the layout decomposition process.
