Innovative Techniques for Pre & Post Layout in VLSI

This technique involves generating schematic diagrams instantly to understand circuit functions. For example, if you have a Verilog code describing a simple AND gate:

p {
module and_gate(input a, input b, output y);
    assign y = a & b;
endmodule
}

The tool can generate a schematic diagram showing how the AND gate works.

Extracting and navigating circuit fragments

This technique allows you to save and reuse parts of your circuit for future simulations. For instance, if you have a complex circuit and you want to reuse a specific part of it in another project, you can extract that part and save it as a separate Spice netlist.

Drag & drop for cross-probing

With this technique, you can easily move elements between different views of your design to speed up the debugging process. For example, if you find an issue in the gate-level view of your design, you can quickly cross-probe to the corresponding part of the RTL view to understand the problem better.

Automatically creating logic symbols

This technique involves automatically generating digital logic symbols and schematics from Spice netlists. For example, if you have a Spice netlist describing a flip-flop, the tool can create a schematic diagram of the flip-flop for easy exploration.

Visualizing post-layout parasitic networks

This technique allows you to analyze parasitic networks in your design after layout. For example, you can use the tool to visualize the parasitic capacitance and resistance in your design and create Spice netlists for critical path analysis.

Recognizing CMOS functions

With this technique, you can easily identify CMOS functions in Spice circuits by turning off parasitic structures. For example, you can remove clutter around transistor symbols to make it easier to understand the circuit. Exporting schematics to Cadence VSE: This technique allows you to export schematics or their fragments into Cadence Virtuoso Schematic Editor for further optimization and debugging. For example, if you find an issue in the schematic view of your design, you can export it to Cadence VSE to make changes.

Read also: Calibre nmLVS Recon | Signoff Verification

Performing ERC checking

This technique involves verifying and debugging connectivity in your design. For example, you can use the tool to identify floating input or output nets, heavily connected nets, and other connectivity issues, especially in structures with multiple fan-ins and fan-outs.

Generating design statistics and reports

With this technique, you can easily generate design statistics and reports to understand the behavior of your design. For example, you can generate reports on the number of gates, the number of connections, and other design metrics.

Extending SpiceVision functionality

This technique allows you to extend the functionality of SpiceVision to match specific project needs. For example, you can use TCL scripts to interface with an open database and customize SpiceVision to meet the requirements of your project.