Calibre nmLVS Recon – A Signoff Verification

The traditional approach to signoff physical verification poses challenges in terms of time consumption and the handling of thousands of transitory errors, which can overwhelm designers and prolong the verification process unnecessarily. Siemens addresses these challenges with Calibre nmLVS Recon by introducing a more iterative and interactive model for early design layout-versus-schematic (LVS) checking.

This model allows engineers to focus on identifying and fixing real and high-impact design errors in the earlier stages of design, without being burdened by transient errors that will disappear as the design matures. By targeting specific checks and utilizing existing LVS databases, Calibre nmLVS Recon enables faster iterations on incomplete and dirty designs, thereby improving verification productivity and turnaround time.

StreamliningIC design

StreamliningIC design(Source)

Electrical Rule Checking (ERC)

Additionally, features such as selective device path checking for Electrical Rule Checking (ERC), enhanced LVS path-finding capability, and interactive debugging tools like Calibre’s RVE interface streamline the debugging process, further accelerating problem diagnosis and resolution. Overall, Calibre nmLVS Recon enhances early stage design LVS checking by providing faster TAT, selective rule file execution, and improved debug productivity, ultimately enabling more efficient verification processes.

Read also: Advanced Reliability Verification : Mentor’s Calibre PERC


Why is it crucial to address violations in signoff checks early in the design cycle?

Addressing violations early prevents them from accumulating and becoming overwhelming during final signoff. By flushing out and resolving issues iteratively throughout implementation flows, designers can minimize turnaround time (TAT) and ensure a smoother tape-out process.

How does Calibre nmLVS Recon support faster LVS iterations on incomplete designs?

Calibre nmLVS Recon enables engineers to focus on core design errors by targeting specific checks like ERC and soft connection checks on incomplete designs. This tool facilitates faster iterations by selectively executing necessary checks from existing LVS databases, eliminating unnecessary analysis of transient errors.

What features does Calibre nmLVS Recon offer to enhance debug productivity during early stage design LVS checking?

Calibre nmLVS Recon provides interactive debugging capabilities and improved diagnostic tools to expedite error diagnosis and resolution. Features such as selective device path checking for ERC, enhanced LVS path-finding, and layer-based rule partitioning optimize run time and memory usage, further streamlining the verification process.

Source: Calibre: Early Design LVS and ERC Checking gets Interesting

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