Synopsys Physical Design Engineer Interview Questions with Answer

Following are Physical Design interview questions with answers

What are the categories in physical verification?

• LVS (Layout versus Schematic)
• DRC (Design Rule Check)
• ERC (Electrical Rule Check)
• LEC (Logical Equivalence Check)

How can you address setup and hold violations simultaneously?

It’s not feasible to fix both simultaneously because enhancing delay in the data path aids hold but hampers setup. However, you can:

• Buffer the data path for hold resolution.
• Reduce the clock frequency for setup resolution (although this isn’t an ideal fix).

How do you prevent cross-talk?

• Increase spacing between the aggressor and victim nets.
• Employ shielding.
• Ensure a stable power supply.
• Enhance the drive strength of the cell.
• Utilize layer jumping.
• Increase the width of the victim net to reduce resistance.
• Implement guard rings.
• Adjust cell sizing (increase size).

What is cross-talk?

Cross-talk refers to the undesirable electric interaction between two or more physically adjacent nets due to capacitance cross-coupling. When two nets are in parallel, the electric field of one net affects the other net, causing the cross-talk effect.

What is scan chain reordering?

Scan chain reordering is the process of rearranging scan chains in the design to optimize routing, thus improving timing and congestion.

Read also: Top 10 Analog Layout Interview Questions(2024)

Explain the concept of rows in floor planning.

Rows in floor planning contain standard cells. All rows have equal height and spacing, but the width of the row can vary. Standard cells in a row receive power and ground connections from VDD and VSS rails. In some cases, rows can be flipped to share power and ground rails.

What are the benefits of NDRs (Non-default Rules)?

• By doubling the width, electromagnetic (EM) issues can be avoided.
• Double spacing helps prevent cross-talk.
• Aids in avoiding congestion at lower metal layers.
• Improves the pin accessibility of standard cells.

Define temperature inversion.

At lower CMOS technologies (below 65nm), cell delay becomes inversely proportional to temperature. However, at higher CMOS technologies, cell delay increases with increasing temperature.

If you encounter a setup problem in a reg-to-reg path, where would you insert a buffer?

Insert a buffer near the launch flop to decrease transition time, thus reducing wire delay and overall delay. Decreasing arrival time reduces setup violations.

What is partitioning?

Partitioning is the process of dividing the chip into smaller blocks to separate different functional blocks and simplify placement and routing.

How can you reduce dynamic power consumption?

• Decrease the power supply voltage.
• Reduce voltage swing in all nodes.
• Lower the switching probability (transition factor).
• Reduce the load capacitance.

Why is double via insertion necessary?

Double via insertion is essential to reduce yield loss due to via failures. Traditionally, double vias are inserted post-route, and then routing is modified to resolve any DRC violations.

What is metal fill insertion?

Metal fill insertion compensates for metal loss during etching. It involves inserting metal fills to prevent excessive metal loss due to chemical reactions.

Define metal slotting.

Metal slotting is a technique used to avoid problems like metal lift-off and metal erosion during the fabrication process.

What are the components of power dissipation?

• Dynamic power consumption: Occurs when signals change logic state, charging or discharging the output node capacitor.
• Static (leakage) power consumption: Power consumed by subthreshold currents and reverse-biased diodes in a CMOS transistor.
• Short-circuit power consumption: Occurs during switching on both NMOS and PMOS transistors simultaneously for a short time.

Explain the dishing effect.

The dishing effect is the difference between the height of the oxide in the spaces and that of the metal in the trenches. It is caused by Chemical Mechanical Polishing (CMP) and may be reduced using dummy fill techniques.

What is CMP (Chemical Mechanical Polishing)?

CMP is a process used to smooth surfaces using a combination of chemical and mechanical forces. It is used in IC fabrication to achieve a high level of planarization.

How are placement blockages useful?

• Defines standard cell and macro areas.
• Reserves channels for buffer insertion.
• Prevents cells from being placed at or near macros.
• Prevents congestion near macros.

What are the types of global routing?

• Time-driven global routing.
• Cross-talk-driven global routing.
• Incremental global routing.

What are the issues resolved in LVS?

• Shorts.
• Opens.
• Missing text layers.
• Missing library in GDS.
• Missing soft layers.

Define clock latency.

Clock latency is the delay between the clock source and clock pin. It includes clock source latency (from the clock source to the definition pin) and clock network latency (from the clock definition pin to the clock pin of the flip-flop).

How do you tackle setup and hold violations?

• For setup: Reduce the number of buffers, replace buffers with 2 inverters, replace HVT cells with LVT cells, increase drive size/strength, insert repeaters, adjust cell position in layout.
• For hold: Add delay in the data path, decrease drive strength in the data path.

What inputs are required for floor planning?

• .v (Verilog)
• .lib and .lef
• .sdc (Synopsys Design Constraints)
• tlu+ file
• Physical partitioning information of the design
• Floor plan parameters like height, width, aspect ratio, utilization
• Pin/pad positions

What are the outcomes of floor planning?

• Die/block area
• I/O pad placements
• Macro placements
• Power grid design
• Power pre-routing
• Standard cell placement area

Explain the concept of keep-out margin.

Keep-out margin is the region around the boundary of fixed macros in the design where no other macros or standard cells are allowed. Only buffers and inverters are allowed in this area.

How do you synthesize a clock tree?

• Single clock: Normal synthesis and optimization.
• Multiple clocks: Synthesize each clock separately.
• Multiple clocks with domain crossing: Synthesize each clock separately and balance the skew