Physical Design Interview Questions of Qualcomm(2024)

Physical Design Interview Questions

The following are Physical Design Interview Questions with answers,

What is IR drop?

IR drop occurs when the current flows through the metal layers in a chip, causing a voltage drop due to resistance.

How can you reduce power dissipation using HVT and LVT in the design?

Use HVT cells when there is positive slack in the path and LVT cells when there is negative slack. HVT cells have higher delay and lower leakage power, while LVT cells have lower delay and higher leakage power.

What is the wire load model (WLM)?

The wire load model estimates delay based on area and fan-out, taking into account resistance, capacitance, and the area of the nets.

What is signal integrity?

Signal integrity refers to the ability of an electrical signal to carry information reliably and resist the effects of high-frequency electromagnetic interference from nearby signals, such as cross-talk and electromagnetic interference (EMI).

Read also: Synopsys Physical Design Interview Questions(2024)

Does cross-talk always lead to violations?

Yes, cross-talk can cause setup or hold violations because it adds or subtracts energy to the signal.

How do positive or negative edge-triggered flip-flops affect setup and hold violations?

Positive edge-triggered flip-flops reduce setup violations, while negative edge-triggered flip-flops reduce hold violations.

What are the inputs and outputs of power planning?


  • Database with a valid floor plan
  • Power rings and power strap widths
  • Spacing between VDD and VSS straps
  • Physical partitioning information of the design
  • Floor plan parameters like height, width, aspect ratio, utilization
  • Pin/pad positions


  • Design with power structure

What are the inputs and outputs of placement?


  • Netlist
  • Mapped and floor-planned design
  • Logical and physical libraries
  • Design constraints


  • Physical layout information
  • Cell placement location
  • Physical layout, timing, and technical information of libraries

If we increase the fan-out of a cell, how does it affect delay?

Increasing fan-out increases the capacitive load on the driving gate, resulting in longer propagation delay.

What are multi-driven nets?

Multi-driven nets are nets with multiple drivers of the same or different signal strengths. Designers should avoid multi-driven nets as they can lead to manufacturing defects and post-silicon verification failures.

What is magnetic placement?

Magnetic placement is a technique used to improve timing or congestion in a design. Fixed objects are specified as magnets, and IC Compiler moves connected standard cells closer to them to optimize placement.

What is a lookup table?

A lookup table is drawn using input transition and output load values. It is used to calculate cell delay.

What do we do for low-power design?

Apply low-power techniques such as clock gating, multi-voltage design, power gating, and multiple VT libraries.

What types of checks are done in PrimeTime?

  • Timing (setup, hold, transition)
  • Design constraints
  • Nets
  • Noise
  • Clock skew

What analysis do we perform during floor planning?

  • Overlapping of macros
  • Allowable IR drop
  • Global route congestion
  • Physical information of the design

What are the different types of delay models?

  • WLM (Wire Load Model)
  • NLDM (Non-Linear Delay Model)
  • CCS (Composite Current Source)

Where are placement blockages created?

  • In floor planning, they act as guidelines for standard cell placement.
  • In clock tree synthesis, blockages are used to reserve space for buffers and inverters.

Why do we apply NDRs in placement?

Applying NDRs in placement helps avoid congestion and timing issues, which are difficult to fix during routing.

What is a mesh?

The horizontal and vertical power straps in the design are called a mesh.

Why are I/O cells placed in the design?

I/O cells interact between the blocks outside of the chip and the internal blocks of the chip. They are placed between the core and the die, providing voltage to the core cells.

What are complex cells in floor planning?

Complex cells are made up of groups of standard cells based on functional requirements. They are taller than standard cells but smaller than macros.

How do you fix Electromigration (EM)?

  • Downsize the driver.
  • Increase metal width.
  • Add more vias.
  • Spread cells.

What is etching?

Etching is used in microfabrication to chemically remove layers from the surface of the wafer during manufacturing.

What is SOI (Silicon On Insulator) technology?

SOI technology refers to the use of layered silicon insulator, which reduces leakage current and power consumption.

What are aggressor and victim nets?

Aggressor: A net that affects a nearby net (victim) due to cross-talk. Victim: A net affected by a nearby net (aggressor) due to cross-talk.

What are Mealy and Moore?

Mealy: Outputs depend on input and present state. Moore: Outputs depend only on the present state

Read also: VLSI Interview Question. 

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