As process technology evolves, designers are confronted with the dual challenges of achieving higher performance and design density while also addressing a multitude of reliability concerns such as Electrostatic Discharge (ESD), Latch-Up (LUP), and Time-Dependent Dielectric Breakdown (TDDB). Traditionally, these reliability issues were addressed during the cell library and technology development stage under specific operation voltage ranges. However, there’s now a shift towards full-chip reliability verification to preempt potential chip reliability failures during burn-in or in silicon.

Role of Standard Cell Libraries in Process Roll-Outs

In the conventional RTL2GDS2 design flow, the standard cell library serves as the initial test vehicle for new process roll-outs due to their relative ease of implementation compared to other macro or custom blocks. Attributes such as timing and power are typically captured in the library and synchronized with the foundry’s provided SPICE model version. Moreover, process variations parameters can also be embedded into the library through extensions like the Liberty Variation Format (LVF).

Intensified Collaboration: Foundries and Designers

The collaboration between foundries and designers has intensified to minimize manufacturing surprises, with Design For Manufacturability (DFM) becoming a norm. Designers strive to incorporate all critical process parameters before tape-out, leveraging the Process Design Kit (PDK) and techfile releases provided by foundries. Similarly, Reliability Design Kits (RDKs) may be supplied, outlining critical design rules as guidelines. However, applying these rules directly to traditional Design Rule Check (DRC) tools presents challenges due to their limitations in identifying electrical current directionality and reliance on physical markers.

Calibre PERC: A Solution for Complex Reliability Verification

Mentor’s Calibre PERC reliability platform addresses these challenges by offering complex reliability verification using both standard foundry rules and project custom rules. It utilizes topological constraints to ensure correct circuit structures are in place as specified by design rules, leveraging netlist and layout information concurrently for electrical checks. The platform employs a Logic-Driven-Layout (LDL) approach, moving away from physical markers to enable more versatile reliability checks.

ESD, LUP, and TDDB Compliance: A Closer Look

Calibre PERC leverages static simulation and voltage propagation features to address ESD, LUP, and TDDB compliance. For ESD prevention, it verifies the existence and strength of ESD protection circuits, ensuring device parameters meet ESD requirements. LUP prevention involves inserting guard rings or straps and maintaining proper spacing among polygons to prevent short-circuit events. Calibre PERC handles LUP checks by annotating voltage values to polygons based on user-defined constraints.

Read also: What is an Integrated Circuit (IC)?

Time-Dependent Dielectric Breakdown (TDDB) Checks

For interconnect TDDB checks, Calibre PERC executes spacing checks among polygons of the same layer but different nets against criteria dependent on voltage range. It propagates external net voltages into internal nets and applies constraints to control static voltage propagation across multiple voltage domains. This comprehensive approach ensures accurate full-chip verification for Design-For-Reliability (DFR) compliance.

In essence, the integration of reliability verification into the design flow, coupled with Mentor’s Calibre PERC platform, enables designers to address the increasing complexities of process technology advancements while ensuring chip reliability through robust verification.