Subthreshold Leakage Reduction in CMOS Digital Circuits

I read that leakage power dissipation will increase 32 times by 2020 due to deep submicron technologies. This affects devices with long idle times, such as smartphones. Forced transistor stacking and input vector control are some methods used to reduce leakage power in active mode by modifying the circuit design to minimize current leakage. This method is effective in lowering leakage during active mode, but it can increase circuit delay and is less effective compared to power gating in standby mode.

Portable devices, like tablets and phones, lose battery power through leakage even when not actively used. Techniques like super cutoff CMOS (SCCMOS) and sleepy stack help by minimizing the leakage during both active and standby modes. SCCMOS adjusts the voltage to reduce leakage without affecting performance much, while sleepy stack combines stacking with sleep transistors for better control.

The super cutoff CMOS (SCCMOS) technique involves under-driving or over-driving the sleep transistors during standby mode. This method provides substantial leakage savings without the need for high-threshold transistors, but it requires a complex controller design to generate the necessary gate voltages.

I've found that leakage power dissipation in CMOS circuits can be managed using various techniques. Power gating is effective in standby mode, and forced stacking is good for active mode. Each technique has trade-offs, like increased delay or dynamic power consumption, but they all aim to extend battery life by reducing unnecessary power loss.