Forum › Category: Layout
Layout
How does dummy insertion impact flicker noise in PMOS current Mirrors?
AnsweredAvatarTechGuru answered 2 months ago • 
275 views3 answers0 votes
In a high-speed ADC layout, how do you mitigate substrate noise coupling when the reference voltage and clock signals share a common metal layer?
AnsweredAvatarDigitalWorld answered 2 months ago • 
262 views3 answers0 votes
Why Setup is checked at max corner and Hold at min corner?
AnsweredAvatarsemiconductor answered 5 months ago • 
1107 views2 answers0 votes
How Do Advanced FinFET Structures Impact the Traditional Physical Design Flow?
AnsweredAvatarsemiconductor answered 5 months ago • 
410 views3 answers0 votes
Can someone explain the device structure and fabrication process of a FinFET?
OpenAvatarCodeBook answered 11 months ago • 
970 views4 answers0 votes
How do you minimize parasitic capacitance in high-frequency analog layouts?
OpenAvatarCodeBook answered 11 months ago • 
624 views4 answers0 votes
How does ion Bombardment affect the Adhesion Process?
OpenAvatarCircuitDesigner answered 10 months ago • 
439 views3 answers0 votes
What is the channeling effect in ion implantation, and how can you prevent it?
OpenAvatarVLSI Master answered 9 months ago • 
535 views2 answers0 votes
In A Reg to Reg Path If You Have Setup Problem Where Will You Insert Buffer-Near to Launching Flop or Capture Flop? Why?
OpenAvatarsemiconductor answered 8 months ago • 
500 views1 answers0 votes
If You Have Both Ir Drop And Congestion How Will You Fix It?
OpenAvatarCircuitDesigner answered 8 months ago • 
475 views2 answers0 votes
How Spacing Helps In Reducing Crosstalk Noise?
OpenAvatarCircuitDesigner answered 8 months ago • 
425 views1 answers0 votes
How Buffer Can Be Used In Victim To Avoid Crosstalk?
OpenAvatarCircuitDesigner answered 8 months ago • 
488 views1 answers0 votes
What is the use of LDD (Lightly Doped Drain) in transistor design?
OpenAvatarCircuitDesigner answered 6 months ago • 
1334 views3 answers0 votes
Shielding should be done with VDD or VSS and on which factors it depends?
OpenAvatarsemiconductor answered 8 months ago • 
715 views1 answers0 votes
What is Latch Up in VLSI?
OpenAvatarsemiconductor answered 8 months ago • 
437 views2 answers0 votes
What is exact reason for different types of ENDCAP/BOUNDARY Cells is used for left and right side edges of macros and core area ?
OpenAvatarDigitalWorld answered 6 months ago • 
470 views2 answers0 votes
How to Solve DIBL?
OpenAvatarsemiconductor answered 10 months ago • 
983 views4 answers2 votes
How does temperature affect transistor characteristics?
AnsweredAvatarsemiconductor answered 6 months ago • 
904 views3 answers4 votes
Let’s assume I have three clock metal routing nets, and I don’t have space in the layout for shielding those three nets, with two of them having the same clock direction. How should I arrange all three, and why?
AnsweredAvatarCircuitDesigner answered 8 months ago • 
624 views1 answers0 votes
Let’s assume I have two clock metal routing nets, and I don’t have space in the layout for shielding those two nets. What should I do?
AnsweredAvatarCircuitDesigner answered 8 months ago • 
407 views1 answers0 votes
12Next »
Ask Question